DS3105_09 datasheet(2/120 Pages) MAXIM

2 / 120 page

_____________________________________________________________________________________________ DS3105

19-4628; Rev 3; 5/09

2 of 120

Table of Contents

STANDARDS COMPLIANCE ..........................................................................................................6

APPLICATION EXAMPLE ...............................................................................................................7

BLOCK DIAGRAM...........................................................................................................................8

DETAILED DESCRIPTION ..............................................................................................................9

DETAILED FEATURES .................................................................................................................10

5.1

INPUT CLOCK FEATURES ...............................................................................................................10

5.2

T0 DPLL FEATURES......................................................................................................................10

5.3

T4 DPLL FEATURES......................................................................................................................10

5.4

OUTPUT APLL FEATURES .............................................................................................................11

5.5

OUTPUT CLOCK FEATURES............................................................................................................11

5.6

GENERAL FEATURES .....................................................................................................................11

PIN DESCRIPTIONS......................................................................................................................12

FUNCTIONAL DESCRIPTION .......................................................................................................16

7.1

OVERVIEW ....................................................................................................................................16

7.2

DEVICE IDENTIFICATION AND PROTECTION .....................................................................................17

7.3

LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION.............................................................17

7.4

INPUT CLOCK CONFIGURATION ......................................................................................................17

7.4.1

Signal Format Configuration ................................................................................................................ 17

7.4.2

Frequency Configuration...................................................................................................................... 18

7.5

INPUT CLOCK MONITORING............................................................................................................19

7.5.1

Frequency Monitoring .......................................................................................................................... 19

7.5.2

Activity Monitoring ................................................................................................................................ 19

7.5.3

Selected Reference Activity Monitoring ............................................................................................... 20

7.6

INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ....................................................................20

7.6.1

Priority Configuration............................................................................................................................ 20

7.6.2

Automatic Selection Algorithm ............................................................................................................. 21

7.6.3

Forced Selection .................................................................................................................................. 21

7.6.4

Ultra-Fast Reference Switching ........................................................................................................... 22

7.6.5

External Reference Switching Mode.................................................................................................... 22

7.6.6

Output Clock Phase Continuity During Reference Switching .............................................................. 22

7.7

DPLL ARCHITECTURE AND CONFIGURATION ..................................................................................23

7.7.1

T0 DPLL State Machine ....................................................................................................................... 24

7.7.2

T4 DPLL State Machine ....................................................................................................................... 27

7.7.3

Bandwidth ............................................................................................................................................ 27

7.7.4

Damping Factor.................................................................................................................................... 28

7.7.5

Phase Detectors................................................................................................................................... 28

7.7.6

Loss-of-Lock Detection ........................................................................................................................ 29

7.7.7

Phase Build-Out ................................................................................................................................... 29

7.7.8

Input to Output (Manual) Phase Adjustment........................................................................................ 30

7.7.9

Phase Recalibration ............................................................................................................................. 30

7.7.10

Frequency and Phase Measurement................................................................................................... 31

7.7.11

Input Jitter Tolerance ........................................................................................................................... 32

7.7.12

Jitter Transfer ....................................................................................................................................... 32

7.7.13

Output Jitter and Wander ..................................................................................................................... 32

7.8

OUTPUT CLOCK CONFIGURATION...................................................................................................33

7.8.1

Signal Format Configuration ................................................................................................................ 33

7.8.2

Frequency Configuration...................................................................................................................... 33

7.9

FRAME AND MULTIFRAME ALIGNMENT ............................................................................................42

7.9.1

Enable and SYNCn Pin Selection........................................................................................................ 42

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