DS3100_09 datasheet(21/227 Pages) MAXIM

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DS3100

19-4546; Rev 9; 5/09

21 of 227

Table 6-7. SPI Bus Mode Pin Descriptions

Note: These pins are active in SPI interface modes. See Section 7.12.2 for functional description and Section 10.6 for timing specifications.

NAME

(1)

TYPE

(2)

FUNCTION

J16

IPU

Active-Low Chip Select.

This pin must be asserted to read or write internal registers.

C16

SCLK

Serial Clock.

SCLK is always driven by the SPI bus master.

D16

SDI

Serial Data Input.

The SPI bus master transmits data to the device on this pin.

E15

SDO

Serial Data Output.

The device transmits data to the SPI bus master on this pin.

D14

CPHA

Clock Phase.

See Figure 7-18.

0 = data is latched on the leading edge of the SCLK pulse

1 = data is latched on the trailing edge of the SCLK pulse

C14

CPOL

Clock Polarity.

See Figure 7-18.

0 = SCLK is normally low and pulses high during bus transactions

1 = SCLK is normally high and pulses low during bus transactions

A15

INTREQ

Interrupt Request.

The behavior of this pin is configured in the INTCR register.

Polarity can be active high or active low. Drive action can be push-pull or open drain.

The pin can also be configured as a general-purpose output if the interrupt request

function is not needed.

Table 6-8. JTAG Interface Pin Descriptions

Note: See Section 9 for functional description and Section 10.7 for timing specifications.

NAME

(1)

TYPE

(2)

FUNCTION

JTRST

IPU

Active-Low JTAG Test Reset.

Asynchronously resets the test access port (TAP)

controller. If not used,

JTRST can be held low or high.

JTCLK

JTAG Clock.

Shifts data into JTDI on the rising edge and out of JTDO on the falling

edge. If not used, JTCLK can be held low or high.

JTDI

IPU

JTAG Test Data Input.

Test instructions and data are clocked in on this pin on the

rising edge of JTCLK. If not used, JTDI can be held low or high.

JTDO

JTAG Test Data Output.

Test instructions and data are clocked out on this pin on the

falling edge of JTCLK. If not used, leave floating.

JTMS

IPU

JTAG Test Mode Select.

Sampled on the rising edge of JTCLK and is used to place

the port into the various defined IEEE 1149.1 states. If not used, connect to VDDIO or

leave floating.

Table 6-9. General-Purpose I/O Pin Descriptions

NAME

(1)

TYPE

(2)

FUNCTION

GPIO1

I/O

General-Purpose I/O Pin 1.

GPCR:GPIO1D configures this pin as an input or an

output. GPCR:GPIO1O specifies the output value. GPSR:GPIO1 indicates the state of

the pin.

GPIO2

I/O

General-Purpose I/O Pin 2.

GPCR:GPIO2D configures this pin as an input or an

output. GPCR:GPIO2O specifies the output value. GPSR:GPIO2 indicates the state of

the pin.

GPIO3

I/O

General-Purpose I/O Pin 3.

GPCR:GPIO3D configures this pin as an input or an

output. GPCR:GPIO3O specifies the output value. GPSR:GPIO3 indicates the state of

the pin.

GPIO4

I/O

General-Purpose I/O Pin 4.

GPCR:GPIO4D configures this pin as an input or an

output. GPCR:GPIO4O specifies the output value. GPSR:GPIO4 indicates the state of

the pin.

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