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SPT7853 датащи(PDF) 1 Page - Cadeka Microcircuits LLC.

номер детали SPT7853
подробное описание детали  TRIPLE 10-BIT, 30 MSPS A/D CONVERTER
PDF  10 Pages
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производитель  CADEKA [Cadeka Microcircuits LLC.]
домашняя страница  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

SPT7853 датащи(HTML) 1 Page - Cadeka Microcircuits LLC.

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SPT7853
TRIPLE 10-BIT, 30 MSPS A/D CONVERTER
BLOCK DIAGRAM
GENERAL DESCRIPTION
The SPT7853 has three 10-bit analog-to-digital converters
on one CMOS chip, each with a sample rate of 30 MSPS.
This device is ideal for professional-level video decoding to
4:2:2/4:4:4 CCIR-601 standard specifications for compo-
nent digital video, including YCrCb and RGB decoding, pro-
fessional video equipment, video frame grabbers, medical
imaging, flat panel display and projection applications.
The SPT7853 offers significant advantages over discrete
single-channel A/D implementations. Board area, package
count, system cost and power dissipation can greatly be
reduced by using a single SPT7853 device. In addition,
several performance advantages exist, including low chan-
nel-to-channel cross-talk noise and well matched channel-
to-channel gain specifications. The three analog-to-digital
converters are driven from a common 2X sample rate
CMOS clock.
The SPT7853 typically consumes only 580 mW of total
power from a single +5 V supply. Digital outputs can operate
with +3 V or +5 V logic and are tri-state capable. The
SPT7853 is offered in a small 52-pin thin quad flat pack
(TQFP) package and operates over the 0 to +70
°C com-
mercial temperature range.
APPLICATIONS
• CCIR-601 (4:2:2/4:4:4) digital component video
• RGB video decoding
• Medical imaging
• Flat panel displays
• PC projectors
FEATURES
• Three 10-bit, 30 MSPS ADCs on one chip
• SINAD of 54.5 dB @ ƒIN = 3.58 MHz
• Channel-to-channel cross talk: –66 dB typical
• Channel-to-channel gain matching of <0.1 dB
• Single 2X sample rate clock
• Total power dissipation: 580 mW (typical)
• Tri-state +3 V to +5 V digital outputs CMOS-compatible
• Single +5 V power supply
Timing
Generation
Reference
Ladder
ADCA
ADCB
ADCC
T/H
T/H
T/H
10
10
10
VINB
DA0–9
Clock
VINA
VINC
DB0–9
DC0–9
VRH Force/Sense
2
VRL Force/Sense
2
Output Enable
Output
Buffer
Output
Buffer
Output
Buffer
DAV


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