SH7262 datasheet(32/45 Pages) RENESAS

32 / 45 page

SH7262/SH7264 Group

High-speed Read/Write Serial Flash Memory

Using the Renesas Serial Peripheral Interface

REJ06B0889-0100/Rev.1.00

June 2009

Page 32 of 45

3.14

Sample Program Listing "serial_flash.c" (11/19)

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/* ==== RSPI ==== */

RSPI0.SPCR.BYTE

0x00;

/* Disables channel 0 of the RSPI */

RSPI0.SPPCR.BYTE

0x30;

/* MOSI idle fixed value = 1 */

RSPI0.SPBR.BYTE

= 0x00;

/* Specifies the base bit rate as 36 MHz

(Bus clock = 72 MHz) */

RSPI0.SPDCR.BYTE

0x20;

/* Disables to transmit the dummy data */

/* Access width to the SPDR register: 8-bit */

RSPI0.SPCKD.BYTE

0x00;

/* RSPCK delay: 1 RSPCK */

RSPI0.SSLND.BYTE

0x00;

/* SSL negate delay: 1 RSPCK */

RSPI0.SPND.BYTE

0x00;

/* Next access delay: 1 RSPCK + 2 Bus clocks */

RSPI0.SPSCR.BYTE

0x00;

/* Sequence length: 1 (SPCMD0 is only used) */

RSPI0.SPCMD0.WORD = 0xE780; /* MSB first */

/* Data length: 8-bit */

/* Keeps the SSL signal level after transfer

is completed */

/* Bit rate: Base bit rate is not divided */

/* RSPCK when idling is 0 */

/* Latches data on odd edge, outputs data on even edge */

RSPI0.SPBFCR.BYTE =

0xC0;

/* Enables to reset data in the

transmit/receive buffer */

RSPI0.SPBFCR.BYTE =

0x00;

/* Disables to reset data in the

transmit/receive buffer */

/* Number of triggers in transmit buffer:

more than one byte available */

/* Number of triggers in receive buffer:

more than one byte received */

RSPI0.SSLP.BYTE

0x00;

/* SSLP = b'0 SSL signal 0-active */

RSPI0.SPCR.BYTE

0x48;

/* Master mode */

/* Disables interrupts */

/* Enables channel 0 of the RSPI */

}

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