LTC4012-1 datasheet(24/28 Pages) LINER

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LTC4012/

LTC4012-1/LTC4012-2

4012f

Figure 12. High Speed Switching Path

4012 F12

VBAT

RSENSE

HIGH

FREQUENCY

CIRCULATING

PATH

BAT

ANALOG

GROUND

SYSTEM

GROUND

SWITCH NODE

CIN

SWITCHING GROUND

COUT

VIN

GND

The LTC4012 can be soft-started with the compensation

capacitor on the ITH pin. At start-up, ITH will quickly rise

to about 0.25V, then ramp up at a rate set by the com-

pensation capacitor and the 40μA ITH bias current. The

full programmed charge current will be reached when ITH

reaches approximately 2V. With a 0.1μF capacitor, the time

to reach full charge current is usually greater than 1.5ms.

This capacitor can be increased if longer start-up times

are required, but loop bandwidth and dynamic response

will be reduced.

INTVDD Regulator Output

Bypass the INTVDD regulator output to GND with a low

ESR X5R or X7R ceramic capacitor with a value of 0.47μF

or larger. The capacitor used to build the BOOST supply

(C2 in Figure 11) can serve as this bypass. Do not draw

more than 30mA from this regulator for the host system,

governed by IC power dissipation.

Calculating IC Power Dissipation

The user should ensure that the maximum rated junction

temperature is not exceeded under all operating conditions.

The thermal resistance of the LTC4012 package (

θJA) is

37°C/W, provided the Exposed Pad is in good thermal

contact with the PCB. The actual thermal resistance in the

application will depend on forced air cooling and other heat

sinking means, especially the amount of copper on the PCB

to which the LTC4012 is attached. The following formula

may be used to estimate the maximum average power dis-

sipation PD (in watts) of the LTC4012, which is dependent

upon the gate charge of the external MOSFETs. This gate

charge, which is a function of both gate and drain voltage

swings, is determined from speciﬁcations or graphs in the

manufacturer’s data sheet. For the equation below, ﬁnd the

gate charge for each transistor assuming 5V gate swing and

a drain voltage swing equal to the maximum VCLP voltage.

Maximum LTC4012 power dissipation under normal op-

erating conditions is then given by:

PD = DCIN(3mA + IDD + 665kHz(QTGATE + QBGATE))

– 5IDD

APPLICATIONS INFORMATION

where:

IDD = Average external INTVDD load current, if any

QTGATE = Gate charge of external top FET in Coulombs

QBGATE = Gate charge of external bottom FET in

Coulombs

PCB Layout Considerations

To prevent magnetic and electrical ﬁeld radiation and

high frequency resonant problems, proper layout of the

components connected to the LTC4012 is essential. Refer

to Figure 12. For maximum efﬁciency, the switch node

rise and fall times should be minimized. The following

PCB design priority list will help insure proper topology.

Layout the PCB using this speciﬁc order.

1. Input capacitors should be placed as close as possible

to switching FET supply and ground connections with

the shortest copper traces possible. The switching

FETs must be on the same layer of copper as the input

capacitors. Vias should not be used to make these

connections.

2. Place the LTC4012 close to the switching FET gate

terminals, keeping the connecting traces short to

produce clean drive signals. This rule also applies to IC

supply and ground pins that connect to the switching

FET source pins. The IC can be placed on the opposite

side of the PCB from the switching FETs.

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