LTC4012 datasheet(23/28 Pages) LINER

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4012f

LTC4012/

LTC4012-1/LTC4012-2

APPLICATIONS INFORMATION

FET Selection

Two external power MOSFETs must be selected for use

with the charger: an N-channel power switch (top FET)

and an N-channel synchronous rectiﬁer (bottom FET).

Peak gate-to-source drive levels are internally set to

about 5V. Consequently, logic-level FETs must be used.

In addition to the fundamental DC current, selection

criteria for these MOSFETs also include channel resis-

tance RDS(ON), total gate charge QG, reverse transfer

capacitance CRSS, maximum rated drain-source voltage

BVDSS and switching characteristics such as td(ON/OFF).

Power dissipation for each external FET is given by:

T R

DTOP

BAT

MAX

DS ON

CLP

()

••

•

()

δΔ

MAX

RSS

DBOT

CLP

BAT

kHz

665

••

•

–•

() =

() AAX

DS ON

CLP

•

()

δΔ

where

δ is the temperature dependency of RDS(ON),

ΔT is the temperature rise above the point speciﬁed in

the FET data sheet for RDS(ON) and k is a constant in-

versely related to the internal LTC4012 top gate driver.

The term (1 +

δΔT) is generally given for a MOSFET in the

form of a normalized RDS(ON) curve versus temperature,

but

δ of 0.005/°C can be used as a suitable approxima-

tion for logic-level FETs if other data is not available.

CRSS = ΔQGD/ΔVDS is usually speciﬁed in the MOSFET

characteristics. The constant k = 2 can be used in estimat-

ing top FET dissipation. The LTC4012 is designed to work

best with external FET switches with a total gate charge

at 5V of 15nC or less.

For VCLP < 20V, high charge current efﬁciency generally

improves with larger FETs, while for VCLP > 20V, top gate

transition losses increase rapidly to the point that using

a topside NFET with higher RDS(ON) but lower CRSS can

actually provide higher efﬁciency. If the charger will be

operated with a duty cycle above 85%, overall efﬁciency

is normally improved by using a larger top FET.

The synchronous (bottom) FET losses are greatest at high

input voltage or during a short circuit, which forces a low

side duty cycle of nearly 100%. Increasing the size of this

FET lowers its losses but increases power dissipation in the

LTC4012. Using asymmetrical FETs will normally achieve

cost savings while allowing optimum efﬁciency.

Select FETs with BVDSS that exceeds the maximum VCLP

voltage that will occur. Both FETs are subjected to this level

of stress during operation. Many logic-level MOSFETs are

limited to 30V or less.

The LTC4012 uses an improved adaptive TGATE and

BGATE drive that is insensitive to MOSFET inertial delays,

td(ON/OFF), to avoid overlap conduction losses. Switching

characteristics from power MOSFET data sheets apply

only to a speciﬁc test ﬁxture, so there is no substitute for

bench evaluation of external FETs in the target application.

In general, MOSFETs with lower inertial delays will yield

higher efﬁciency.

Diode Selection

A Schottky diode in parallel with the bottom FET and/or

top FET in an LTC4012 application clamps SW during the

non-overlap times between conduction of the top and

bottom FET switches. This prevents the body diode of the

MOSFETs from forward biasing and storing charge, which

could reduce efﬁciency as much as 1%. One or both diodes

can be omitted if the efﬁciency loss can be tolerated. A 1A

Schottky is generally a good size for 3A chargers due to the

low duty cycle of the non-overlap times. Larger diodes can

actually result in additional efﬁciency (transition) losses

due to larger junction capacitance.

Loop Compensation and Soft-Start

The three separate PWM control loops of the LTC4012

can be compensated by a single set of components at-

tached between the ITH pin and GND. As shown in the

typical LTC4012 application, a 6.04k resistor in series

with a capacitor of at least 0.1μF provides adequate loop

compensation for the majority of applications.

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