System description

STA2065

8/20

Doc ID16050 Rev 1

2.5.2

Sample rate converter (SaRaC)

This block offers a fully digital stereo asynchronous sample rate conversion, using an

automatic Digital Ratio Locked Loop. Its main features are:

–

Up to 20-bit input and 22-bit output sample size

–

DMA optimized 16-bit stereo sample interface

–

Input sample rate from selectable MSP or SPDIF interface (32 kHz to 48 kHz)

–

Output sample rate from selectable MSP interface (44.1 kHz to 48 kHz)

–

Internally generated input sample rate (8 kHz to 48 kHz) for compressed audio

decoding

2.5.3

JPEG decoder

The JPEG decoder block performs Baseline DCT sequential decoding up to 16Mpix/sec.

JPEG compressed thumbnails are also supported.

2.5.4

Video input

STA2065 has a Video Input Port. The VIP allows to grab images from external devices,

supporting parallel CCIR-656 interface up to 80 MHz.

This block can be used in camera mode with an imaging co-processor or a CVBS video

decoder to store pixel information into system memory. It can be also used in raw mode to

directly store raw data from external sensor.

2.5.5

Smart graphics accelerator (SGA)

The smart graphics accelerator (SGA) provides an efficient 2D and 3D primitive drawing tool

that breaks down the MIPS and power consumption concerns of pixel processing.

2.5.6

Color LCD controller (CLCD)

This interface drives LCD panels. It supports single or dual-panel color and monochrome

STN displays and color TFT or HR-TFT displays. The resolution can be 1, 2 or 4 bits-

perpixel (bpp) palletized for mono STN, 1, 2, 4 or 8 bpp palletized for color STN and TFT,

16-bpp true-color non palletized for Color STN and TFT, 24-bpp packed or not packed

truecolor non pallettized for color TFT. It also offers Frame Modulation to deliver enhanced

colors on 12, 16 or 18 bits (HR-) TFT panels from up to 24-bpp format.