TUSB2043

4-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS308A – FEBRUARY 1999 – REVISED AUGUST 1999

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BUSPWR

8

I

Power source indicator. BUSPWR is an active high input that indicates whether the downstream ports source

their power from the USB cable or a local power supply. For the bus-power mode, this pin should be pulled

to 3.3 V, and for the self-powered mode, this pin should be pulled low. This standard TTL input must not change

dynamically during operation.

DM0

2

I/O

Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.

DM1 – DM4

11, 15,

19, 23

I/O

USB differential data minus. DM1 – DM4 paired with DP1 – DP4 support up to four downstream USB ports.

DP0

1

I/O

Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.

DP1 – DP4

12, 16,

20, 24

I/O

USB differential data plus. DP1 – DP4 paired with DM1 – DM4 support up to four downstream USB ports.

EECLK

5

O

EEPROM serial clock. When EXTMEM is high, the EEPROM interace is disabled. The EECLK pin is disabled

and should be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial clock output

to the EEPROM with a 100

µA internal pulldown.

EEDATA/

GANGED

6

I/O

EEPROM serial data/power management mode indicator. When EXTMEM is high, EEDATA/GANGED selects

between gang or per-port power over-current detection for the downstream ports. When EXTMEM is low,

EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100

µA

pulldown. This standard TTL input must not change dynamically during operation.

EXTMEM

26

I

EEPROM read enable. When EXTMEM is high, the serial EEPROM interface of the device is disabled. When

EXTMEM is low, terminals 5 and 6 are configured as the clock and data pins of the serial EEPROM interface,

respectively.

GND

7, 28

Ground. GND terminals must be tied to ground for proper operation.

OVRCUR1 –

OVRCUR4

10, 14,

18, 22

I

Over-current inputs. OVRCUR1 – OVRCUR4 are active low, standard TTL inputs. For per-port over current

detection, one over-current input is available for each of the four downstream ports. In the ganged mode, any

OVRCUR input may be used and all OVRCUR pins should be tied together. OVRCUR pins are active low

inputs with noise filtering logic.

PWRON1 –

PWRON4

9, 13,

17, 21

O

Power-on/-off control signals. PWRON1 – PWRON4 are active low, push-pull outputs. Push-pull outputs

eliminate the pullup resistors which open-drain outputs require. However, the external power switches that

connect to these pins must be able to operate with 3.3 V inputs because these outputs cannot drive 5 V signals.

RESET

4

I

Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET

is asserted, all logic is initialized.

SUSPND

32

O

Suspend status. SUSPND is an active high output available for external logic power down operations. During

the suspend mode, SUSPND is high. SUSPND is low for normal operation.

MODESLCT

31

I

Mode select pin. With a simple RC circuit, this pin ensures the normal operation mode is selected. Refer to

application information section for detailed information.

CLKIN

27

I

48 MHz clock input. Tie this pin to the output of the oscillator.

VCC

3, 25

3.3-V supply voltage

TESTIN

30

I

Test input pin. This pin is used as a test input pin during production test. TESTIN must be tied to VCC (3.3 V)

for normal operation.

TESTOUT

29

O

Test output pin. This pin is used as a test output pin during production test. TESTOUT must be left open during

normal operation.