PCM1795DB datasheet(24/58 Pages) TI

24 / 58 page

Slave Address

MSB

LSB

ADR1

ADR0

R/W

Packet Protocol

SDA

SCL

Start

Condition

Stop

Condition

SlaveAddress

ACK

DATA

ACK

DATA

ACK

R/W

ReadOperation

Transmitter

DataType

SlaveAddress

ACK

DATA

ACK

DATA

ACK

NACK

WriteOperation

Transmitter

DataType

SlaveAddress

ACK

DATA

ACK

DATA

ACK

R/ :ReadOperationif1;Otherwise,WriteOperation

ACK:AcknowledgmentofaByteif0

NACK:NotAcknowledgedif1

DATA:8Bits(Byte)

M:MasterDevice

S:SlaveDevice

St:StartCondition

Sp:StopCondition

R:Read

:Write

ACK:Acknowledge

NACK:NotAcknowledged

PCM1795

SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com

The PCM1795 has seven bits for its own slave address, as shown in Figure 44. The first five bits (MSBs) of the

slave address are factory preset to 10011. The next two bits of the address byte are the device select bits that

can be user-defined by the ADR1 and ADR0 terminals. A maximum of four PCM1795s can be connected on the

same bus at one time. Each PCM1795 responds when it receives its own slave address.

Figure 44. Slave Address

A master device must control packet protocol that consists of a start condition, slave address, read/write bit, data

if write or acknowledge if read, and stop condition. The PCM1795 supports only slave receivers and slave

transmitters.

Figure 45. Basic I2C Framework

Submit Documentation Feedback

Product Folder Link(s): PCM1795

PCM1795DB датащи(PDF) 24 Page - Texas Instruments

PCM1795DB датащи(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

датащи скачать

ссылки URL