INA220 datasheet(9/35 Pages) TI

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APPLICATION INFORMATION

INA220 TYPICAL APPLICATION

Serial Bus Address

BUS OVERVIEW

INA220

www.ti.com ............................................................................................................................................................. SBOS459B – JUNE 2009 – REVISED JUNE 2009

The INA220 is a digital current-shunt monitor with an

Data transfer is then initiated and eight bits of data

Two-Wire

and

SMBus-compatible

interface.

are sent, followed by an Acknowledge bit. During

provides digital current, voltage, and power readings

data transfer, SDA must remain stable while SCL is

necessary

for

accurate

decision-making

HIGH. Any change in SDA while SCL is HIGH is

precisely-controlled systems. Programmable registers

interpreted as a START or STOP condition.

allow

flexible

configuration

for

measurement

resolution,

and

continuous-versus-

Once all data have been transferred, the master

triggered operation. Detailed register information

generates a STOP condition, indicated by pulling

appears at the end of this data sheet, beginning with

SDA from LOW to HIGH while SCL is HIGH. The

Table 2. See the Register Block Diagram for a block

INA220 includes a 28ms timeout on its interface to

diagram of the INA220.

prevent locking up an SMBus.

The figure on the front page shows a typical

To communicate with the INA220, the master must

application circuit for the INA220. Use a 0.1

µF

first address slave devices via a slave address byte.

ceramic capacitor for power-supply bypassing, placed

The slave address byte consists of seven address

as closely as possible to the supply and ground pins.

bits, and a direction bit indicating the intent of

executing a read or write operation.

The input filter circuit consisting of RF1, RF2, and CF is

not necessary in most applications. If the need for

The INA220 has two address pins, A0 and A1.

filtering is unknown, reserve board space for the

Table 1 describes the pin logic levels for each of the

components and install 0

Ω resistors unless a filter is

16 possible addresses. The state of pins A0 and A1

needed. See the Filtering and Input Considerations

is sampled on every bus communication and should

section.

be set before any activity on the interface occurs. The

address

pins

are

read

the

start

each

communication event.

The INA220 offers compatibility with both Two-Wire

Table 1. INA220 Address Pins and

and SMBus interfaces. The Two-Wire and SMBus

Slave Addresses

protocols are essentially compatible with one another.

SLAVE ADDRESS

The Two-Wire interface is used throughout this data

GND

1000000

sheet as the primary example, with SMBus protocol

GND

VS+

1000001

specified only when a difference between the two

GND

SDA

1000010

systems is being addressed. Two bidirectional lines,

GND

SCL

1000011

SCL and SDA, connect the INA220 to the bus. Both

SCL and SDA are open-drain connections.

VS+

GND

1000100

VS+

1000101

The device that initiates the transfer is called a

master, and the devices controlled by the master are

VS+

SDA

1000110

slaves. The bus must be controlled by a master

VS+

SCL

1000111

device that generates the serial clock (SCL), controls

SDA

GND

1001000

the bus access, and generates START and STOP

SDA

VS+

1001001

conditions.

SDA

1001010

To address a specific device, the master initiates a

SDA

SCL

1001011

START condition by pulling the data signal line (SDA)

SCL

GND

1001100

from a HIGH to a LOW logic level while SCL is HIGH.

SCL

VS+

1001101

All slaves on the bus shift in the slave address byte

on the rising edge of SCL, with the last bit indicating

SCL

SDA

1001110

whether a read or write operation is intended. During

SCL

1001111

the ninth clock pulse, the slave being addressed

responds

the

master

generating

Acknowledge and pulling SDA LOW.

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