TPS70745, TPS70748, TPS70751, TPS70758, TPS70702

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

SLVS291 – MAY 2000

2

POST OFFICE BOX 655303

description (continued)

The TPS707xx family of voltage regulators offers very low dropout voltage and dual outputs with power up

sequence control, which is designed primarily for DSP applications. These devices have extremely low noise

output performance without using any added filter bypass capacitors and are designed to have a fast transient

response and be stable with 10 uF low ESR capacitors.

These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable/adjustable voltage

options. Regulator 1 can support up to 250 mA and regulator 2 can support up to 125 mA. Separate voltage

inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV

on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is

a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of

230

µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal

to EN (enable) shuts down both regulators, reducing the input current to 1

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is

source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator

is turned off(disabled).

The PG1 pin reports the voltage conditions at VOUT1. Power good can be used to implement a SVS for the

circuitry supplied by regulator 1.

The TPS707xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP

systems and related digital applications in the event of an undervoltage condition. RESET indicates the status

MR1 and MR2 are in the logic high state, RESET will go to a high impedance state after 120 ms delay. RESET

The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until

VIN1 reaches 2.5V.

AVAILABLE OPTIONS

TJ

REGULATOR 1

VO (V)

REGULATOR 2

VO (V)

TSSOP

(PWP)

3.3 V

1.2 V

TPS70745PWP

3.3 V

1.5 V

TPS70748PWP

–40

°Cto125°C

3.3 V

1.8 V

TPS70751PWP

– 40

°C to 125°C

3.3 V

2.5 V

TPS70758PWP

Adjustable

(1.22 V to 5.5 V)

Adjustable

(1.22 V to 5.5 V)

TPS70702PWP

NOTE: The TPS70702 is programmable using external resistor dividers (see

application information) The PWP package is available taped and reeled. Add

an R suffix to the device type (e.g., TPS70702PWPR).