September 2006

PCS2I99448

rev 0.4

3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

11 of 15

Notice: The information in this document is subject to change without notice.

PCLK

PCLK

GND

CCLK

GND

GND

GND

GND

The pin-to-pin skew is defined as the worst case

difference in propagation between any similar delay path

within a single device

CCLK

GND

GND

GND

The time from the output controlled edge to the

non-controlled edge, divided by the time output

controlled edge, expressed as a percentage.

2.4

1.8V

0.5

0.6V

The variation in cycle time of a single between adjacent

cycles, over a random sample of adjacent cycle pairs

CCLK

PCLK

GND

GND

CLK_STOP

Figure 16. Output Transition Time Test Reference

Figure 15. Output Duty Cycle (DC)

Figure 17. Cycle–to–Cycle Jitter Reference