TMS77C82 datasheet(21/73 Pages) TI

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TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

low-power and IDLE modes (continued)

In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial

communications interface remain active. System processing is suspended until a qualified interrupt (hardware

RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial

communications interface) is detected.

In the HALT mode (HALT/STANDBY = 1), the TMS370Cx6x is placed in its lowest power-consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level

on the receive pin of the serial communications interface) is detected. The low-power mode selection bits are

summarized in Table 13.

Table 13. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

MODE SELECTED

STANDBY

HALT

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6– 7 bits is ignored. In addition, if an idle instruction executes when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is automatically enabled

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This

means that the NMI always is generated, regardless of the interrupt-enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status

registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the

STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘x6x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard

oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of

a TMS370 microcontroller. The ‘x6x ROM-masked devices offer both options to meet system engineering

requirements. Only one of the two clock options is allowed on each ROM device. An EPROM has only the

divide-by-1.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a 1-to-1 match between the external resonator frequency and the internal system clock

(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external

resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock

module then divides the resulting signal by four to provide the four-phased internal system clock signals. The

resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows:

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