TMS320VC5420 datasheet(13/77 Pages) TI

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TMS320VC5420

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS080C – MARCH 1999 – REVISED APRIL 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Signal Descriptions (Continued)

NAME

DESCRIPTION

TYPE†

HOST-PORT INTERFACE SIGNALS (CONTINUED)

PRIMARY

HCNTL0

HCNTL1

PPA3

PPA2

HPI control inputs. The HCNTL0 and HCNTL1 values between HPIA, and HPID registers

during HPI reads and writes. These signals are only used in HPI multiplexed address/data

mode (HMODE pin is low).

These pins are shared with the external memory interface and are only used by the HPI

when the interface is in HPI mode (XIO pin is low).

HAS‡§

PPA4‡§

Address strobe input. Hosts with multiplexed address and data pins require HAS to latch

the address in the HPIA register. This signal is only used in HPI multiplexed address/data

mode (HMODE pin is low).

This pin is shared with the external memory interface and is only used by the HPI when

the interface is in HPI mode (XIO pin is low).

HCS‡§

MSTRB‡§

HPI chip-select signal. Thissignal must be active during HPI transfers, and can remain

active between concurrent transfers.

This pin is shared with the external memory interface and is only used by the HPI when

the interface is in HPI mode (XIO pin is low).

HDS1‡§

HDS2‡§

PS‡§

DS‡§

HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes to control

transfer HPI transfers.

These pins are shared with the external memory interface and are only used by the HPI

when the interface is in HPI mode (XIO pin is low).

HR/W

R/W

HPI read/write signal. This signal is used by the host to control the direction of an HPI

transfer.

This pin is shared with the external memory interface and is only used by the HPI when

the interface is in HPI mode (XIO pin is low).

HRDY

READY

HPI data-ready output. The ready output informs the host when the HPI is ready for the

next transfer.

This pin is shared with the external memory interface and is only used by the HPI when

the interface is in HPI mode (XIO pin is low). HRDY is placed into the high-impedance state

when OFF is low.

A_HINT

B_HINT

PPA0

PPA1

Host interrupt pin. HPI can interrupt the host by asserting this low. The host can clear this

interrupt by writing a “1” to the HINT bit of the HPIC register. Only supported in HPI

multiplexed address/data mode (HMODE pin is low). These pins are placed into the

high-impedance state when OFF is low.

HPIRS§

Host-port interface (HPI) reset pin. This signal resets the host port interface and both subsystems.

HMODE

Host mode select. When this pin is low it selects the HPI multiplexed address/data mode. The multiplexed

address/data mode allows hosts with multiplexed address/data lines access to the HPI registers HPIC, HPIA,

and HPID. Host-to-DSP and DSP-to-host interrupts are supported in this mode.

When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts with

separate address/data buses to access the HPI address range by way of the 18-bit address bus and the HPI data

(HPID) register via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not supported in this mode.

SUPPLY PINS

AVDD

Dedicated power supply that powers the PLL. AVDD = 1.8 V. AVDD can be connected to CVDD.

CVDD

Dedicated power supply that powers the core CPUs. CVDD = 1.8 V

DVDD

Dedicated power supply that powers the I/O pins. DVDD = 3.3 V

VSS

Digital ground. Dedicated ground plane for the device.

† I = Input, O = Output, S = Supply, Z = High Impedance

‡ This pin has an internal pullup resistor.

§ These pins have Schmitt trigger inputs.

¶ This pin has an internal bus holder controlled by way of the BSCR register in subchip A.

# This pin is used by Texas Instruments for device testing and should be left unconnected.

|| This pin has an internal pulldown resistor.

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