TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

15

POST OFFICE BOX 655303

APPLICATION INFORMATION

hardware interfacing

Figure 18 shows an example of how to connect the TLV5616 to an MCS51® compatible microcontroller. The

serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent

on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide

the chip select and frame sync signals for the TLV5616.

SDIN

SCLK

CS

OUT

REFIN

AGND

REF

RxD

TxD

P3.4

MCS51® Controller

TLV5616

FS

P3.5

VDD

RLOAD

Figure 18. TLV5616 to MCS51® Controller Interface

software

The example program puts out a sine wave on the OUT pin.

The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine fetches

and writes the next sample to the DAC. The samples are stored in a lookup table, which describes one full period

of a sine wave.

The serial port of the controller is used in mode 0, which transmits 8 bits of data on RxD, accompanied by a

synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the

TLV5616. The CS and FS signals are provided in the required fashion through control of I/O port 3, which has

bit addressable outputs.

;***************************************************************************************

;* Title

: Ramp generation with TLV5616

*

;* Version : 1.0

*

;* MCU

*

;*

© (1998) Texas Instruments Incorporated

*

;***************************************************************************************

;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

; Program function declaration

;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

NAME

GENSINE

MAIN

SEGMENT

CODE

ISR

SEGMENT

CODE

SINTBL SEGMENT

CODE

VAR1

SEGMENT

DATA

STACK

SEGMENT

IDATA

;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

; Code start at address 0, jump to start

;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

CSEG AT

0

MCS is a registered trademark of Intel Corporation