TLV320AD11A

3.3 V INTEGRATED ADSL OVER POTS CODEC

SLWS087B – JUNE 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ADR0

ADR1

54

55

I

Serial port chip ID address bits, ADR0 is the least significant bit.

AVDD1_EC

60

I

EC channel analog power supply #1

AVDD2_EC

64

I

EC channel analog power supply #2

AVDD1_TX

66

I

TX channel analog power supply #1

AVDD2_TX

70

I

TX channel analog power supply #2

AVDD_ADC

12

I

Receive channel analog power supply

AVDD_FIL_EC

73

I

EC channel filter analog power supply

AVDD_FIL_RX

93

I

Receive channel filter analog power supply

AVDD_FIL_TX

83

I

Transmit channel filter analog power supply

AVDD_REF

86

I

Reference analog power supply

AVSS1_EC

61

I

EC channel analog ground # 1

AVSS2_EC

65

I

EC channel analog ground #2

AVSS1_TX

67

I

TX channel analog ground #1

AVSS2_TX

71

I

TX channel analog ground #2

AVSS_ADC

13

I

Receive channel analog ground

AVSS_FIL_EC

72

I

EC channel filter analog ground

AVSS_FIL_RX

94

I

Receive channel filter analog ground

AVSS_FIL_TX

84

I

Transmit channel filter analog ground

AVSS_REF

87

I

Reference analog ground

CLKIN

42

I

35.328 MHz VCXO clock input

CLKOUT/INT

41

O

If CONFIG2 (pin 100) is low, this pin is 4.416 MHz clock output. If CONFIG2 is high, this pin functions as

INT.

COMPA_EC

63

O

EC channel cap input A. Add 500 pF X7R ceramic capacitor to AVDD1_EC.

COMPB_EC

62

O

EC channel cap input B. Add 1

µF X7R ceramic capacitor to AVDD1_EC.

COMPA_TX

68

O

TX channel decoupling cap input A. Add 500 pF ceramic capacitor to AVDD1_TX.

COMPB_TX

69

O

TX channel decoupling cap input B. Add 1

µF ceramic capacitor to AVDD1_TX.

CONFIG2

100

I

I/O configuration input pin. A high on this pin redefines the function of pins 37 and 41. The default state of

this pin is low. Refer to Figure 3 for details.

CS

51

I

Parallel port chip select

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

34 (MSB)

33

32

31

30

29

28

25

24

23

22

21

20

19

18

17 (LSB)

I/O

Parallel port data bits D0=LSB