TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

shift register latch for brightness control and OVM

The shift register latch for both brightness control and OVM (Output Voltage Monitor) is configured with a

1 x 1 byte. In the shift register latch for brightness control, the division ratio of GSCLK can be set and the output

current value on the constant current output can be adjusted. In the shift register latch for OVM, the comparison

voltage at OVM comparator on the constant current output terminals (OUT0 to OUT15) can be set and the output

signal for both XDOWN1 and XDOWN2 can be forced to low level. When power up, the latch data is

indeterminate and the shift register is not initialized. Data should be written to the shift register latch prior to

turning the constant current output on (BLANK=L) when these functions are used. Also, it is inhibited to rewrite

the latch value for brightness control when the constant current output is turned on. When these functions are

not used, the latch value can be set to the default value setting BCENA or MCENA to low level (tied to GND).

The configuration of the shift register and the latch for brightness control and monitor control is shown in below.

XLATCH

Latch for Brightness Control

DOUT0 to 7

DIN0 to 7

DCLK

GSCLK Division Ratio Data Set

00

0

1

1

1

1

1

MSB

LSB

MSB

LSB

Shift Register for Brightness Control

DIN7

DATA

DIN6

DATA

DIN5

DATA

DIN4

DATA

DIN3

DATA

DIN2

DATA

DIN1

DATA

DIN0

DATA

(Note A)

GSCLK Division Ratio Data Set

Current Data Adjusted On Constant Current Output

XLATCH

N/A

00

0

1

MSB

LSB

(Note B)

Latch for OVM

Monitor Control Data

Note A: Indicates default value at the BCENA terminal = 0 if the brightness control latch = 1

DOUT0 to 7

DIN0 to 7

DCLK

Shift Register for OVM

DIN7

DATA

DIN6

DATA

DIN5

DATA

DIN4

DATA

DIN3

DATA

DIN2

DATA

DIN1

DATA

DIN0

DATA

Note B: Indicates default value at the MCENA terminal = 0 if the OVM latch =1

Figure 4. Relationship Between Shift Register and Latch for Brightness Control and OVM

write data to shift register latch

The shift register latch written to is selected using the RSEL0 and RSEL1 terminals. The data is applied to the

DIN data input terminal and is clocked into the shift register synchronizing to the rising edge of DCLK after

XENABLE is pulled low. The shift register for the gray scale data is 8 bits length at 8 bit mode resulting in eight

times DCLK, and 16 bit length at 16 bit mode resulting in sixteen times DCLK, and as for the brigtness control

and monitor control resulting one times DCLK input. At the number of DCLK input for each case, data can be

written into the shift register. In this condition, when XLATCH is pulled high, data in the shift register is clocked

into the latch (data through), and when XLATCH is pulled low, the data is held (latch).