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TLC545CFN датащи(PDF) 7 Page - Texas Instruments

номер детали TLC545CFN
подробное описание детали  8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS
PDF  13 Pages
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производитель  TI [Texas Instruments]
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TLC545CFN датащи(HTML) 7 Page - Texas Instruments

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TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC545 or 1.1 MHz for TLC546,
fclock(SYS) = 4 MHz for TLC545 or 2.1 MHz for TLC546
PARAMETER
TEST CONDITIONS
TLC545
TLC546
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
EL
Linearity error
See Note 5
±0.5
±0.5
LSB
EZS
Zero-scale error
See Note 6
±0.5
±0.5
LSB
EFS
Full-scale error
See Note 6
±0.5
±0.5
LSB
Total unadjusted error
See Note 7
±0.5
±0.5
LSB
Self-test output code
INPUT A19 address = 10011
(see Note 8)
01111101
(125)
10000011
(131)
01111101
(125)
10000011
(131)
tconv
Conversion time
See Operating Sequence
9
17
µs
Total access and
conversion time
See Operating Sequence
13
25
µs
tacq
Channel acquisition time
(sample cycle)
See Operating Sequence
3
3
I/O
clock
cycles
tv
Time output data remains
valid after I/O CLOCK
10
10
ns
td
Delay time, I/O CLOCK to
DATA OUT valid
300
400
ns
ten
Output enable time
See Parameter
150
150
ns
tdis
Output disable time
See Parameter
Measurement Information
150
150
ns
tr(bus)
Data bus rise time
300
300
ns
tf(bus)
Data bus fall time
300
300
ns
NOTES:
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The INPUT A19 analog input signal is internally
generated and is used for test purposes.



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