TLC545C, TLC545I, TLC546C, TLC546I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 19 INPUTS

SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996

5

POST OFFICE BOX 655303

recommended operating conditions

TLC545

TLC546

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

Supply voltage, VCC

4.75

5

5.5

4.75

5

5.5

V

Positive reference voltage, Vref+ (see Note 2)

0

VCC VCC +0.1

0

VCC VCC +0.1

V

Negative reference voltage, Vref– (see Note 3)

– 0.1

0

VCC

– 0.1

0

VCC

V

Differential reference voltage, Vref+ – Vref– (see Note 3)

0

VCC VCC +0.2

0

VCC VCC +0.2

V

Analog input voltage (see Note 3)

0

VCC

0

VCC

V

High-level control input voltage, VIH

2

2

V

Low-level control input voltage, VIL

0.8

0.8

V

Setup time, address bits at data input before I/O CLOCK

↑,

tsu(A)

200

400

ns

Address hold time, th

0

0

ns

Setup time, CS low before clocking in first address bit, tsu(CS)

(see Note 2)

3

3

System

clock

cycles

I/O CLOCK frequency, fclock(I/O)

0

2.048

0

1.1

MHz

SYSTEM CLOCK frequency, fclock(SYS)

fclock(I/O)

4

fclock(I/O)

2.1

MHz

Pulse duration, CS high during conversion, twH(CS)

36

36

System

clock

cycles

Pulse duration, SYSTEM CLOCK high, twH(SYS)

110

210

ns

Pulse duration, SYSTEM CLOCK low, twL(SYS)

100

190

ns

Pulse duration, I/O CLOCK high, twH(I/O)

200

404

ns

Pulse duration, I/O CLOCK low, twL(I/O)

200

404

ns

System

fclock(SYS) ≤ 1048 kHz

30

30

ns

Clock transition time

System

fclock(SYS) > 1048 kHz

20

20

ns

(see Note 4)

I/O

fclock(I/O) ≤ 525 kHz

100

100

ns

I/O

fclock(I/O) > 525 kHz

40

40

ns

Operating free air temperature TA

TLC545C, TLC546C

0

70

0

70

Operating free-air temperature, TA

TLC545I, TLC546I

–40

85

–40

85

°C

NOTES:

2. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling

edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address

data until the minimum chip select setup time has elapsed.

3. Analog input voltages greater than that applied to REF+ convert as all “1”s (11111111), while input voltages less than that applied

to REF– convert as all “0”s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends

to increase.

4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity

of normal room temperature, the devices function with input clock transition time as slow as 2

µs for remote data acquisition

applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.