TLC32040M

ANALOG INTERFACE CIRCUIT

POST OFFICE BOX 655303

4–2

description (continued)

The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic transitional)

low-pass and high-pass filters, respectively, and a fourth-order equalizer. The input filter is implemented in

switched-capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing

caused by sampled data filtering. When no filtering is desired, the entire composite filter can be switched out

of the signal path. A selectable, auxiliary, differential analog input is provided for applications where more than

one analog input is required.

The A/D and D/A converters each have 14 bits of resolution. The A/D and D/A architectures ensure no missing

codes and monotonic operation. An internal voltage reference is provided on the TLC32040M to ease the design

task and to provide complete control over the performance of the integrated circuit. The internal voltage

reference is brought out to a pin and is available to the designer. Separate analog and digital voltage supplies

and grounds are provided to minimize noise and ensure a wide dynamic range. Also, the analog circuit path

contains only differential circuitry to keep noise to an absolute minimum. The only exception is the DAC sample

and hold, which utilizes pseudo-differential circuitry.

The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter with

a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed by a

continuous-time filter to eliminate images of the digitally encoded signal.

The TLC32040M is characterized for operation from – 55

°C to 125°C.

functional block diagram

IN +

IN –

AUX

IN +

AUX

IN –

M

U

X

X

U

M

Band-Pass Filter

Receive Section

OUT +

Transmit Section

D/A

A/D

Serial

Port

Low-Pass Filter

Internal

Voltage

Reference

FSR

DR

EODR

MSTR CLK

SHIFT CLK

WORD/BYTE

DX

FSX

EODX

ANLG

GND

REF

RESET

OUT–

26

25

24

23

22

21

VCC + VCC –

DTGL

GND

VDD

(DIG)

20

19

18

9

7

8

2

4

5

3

6

10

13

12

14

11