TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MAY 1999

13

POST OFFICE BOX 655303

functional description (continued)

programmable baud rate generator

The TL16C752 UART contains a programmable baud generator that takes any clock input and divides it by a

the internal baud rate generator. The output frequency of the baud rate generator is 16x the baud rate. The

formula for the divisor is:

divisor = (XTAL1 crystal input frequency/prescaler) / (desired baud rate

× 16)

Where:

prescaler

+

1, when MCR[7] is set to 0 after reset (1X clock selected)

4, when MCR[7] is set to 1 after reset (1X 4 clock selected)

Figure 9 shows the internal prescaler and baud rate generator circuitry.

Prescaler Logic

(Divide By 1)

Prescaler Logic

(Divide By 4)

Internal

Oscillator

Logic

Bandrate

Generator

Logic

XTAL1

XTAL2

Internal

Bandrate Clock

For Transmitter

and Receiver

MCR[7] = 0

MCR[7] = 1

Figure 9. Prescaler and Baud Rate Generator Block Diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and

most significant byte of the baud rate divisor.

Writing to the divisor registers, DLL or DLH, may result in wait states being inserted during the write access while

the baud rate generator is loaded with the new value. Note that if DLL and DLH are both zero, the UART is

effectively disabled, as no baud clock will be generated.

NOTE:

The programmable baud rate generator is provided to select both the transmit and receive clock

rates.

Table 5 and Table 6 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and

3.072 MHz respectively.

Figure 10 and Figure 11 show the crystal clock circuit reference.