SN74LVC125A

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCAS290F – JANUARY 1993 – REVISED JUNE 1998

1

POST OFFICE BOX 655303

CMOS) Submicron Process

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

Small-Outline (D), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE) input is high.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

The SN74LVC125A is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE

A

Y

L

H

H

L

LL

H

X

Z

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

D, DB, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y