LTC2232 datasheet(21/28 Pages) LINER

21 / 28 page

LTC2232/LTC2233

22323fa

The lower limit of the LTC2232/LTC2233 sample rate is

determined by droop of the sample-and-hold circuits. The

pipelined architecture of this ADC relies on storing analog

signals on small valued capacitors. Junction leakage will

discharge the capacitors. The specified minimum operat-

ing frequency for the LTC2232/LTC2233 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits and the overflow bit.

APPLICATIO S I FOR ATIO

Figure 12a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Digital Output Buffers

Figure 13 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional N-

channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50

Ω to external

circuitry and may eliminate the need for external damping

resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2232/LTC2233 should drive a

minimal capacitive load to avoid possible interaction be-

tween the digital outputs and sensitive input circuitry. The

output should be buffered with a device such as an

ALVCH16373 CMOS latch. For full speed operation the

capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Figure 12b. ENC Drive Using a CMOS to PECL Translator

22323 F12a

ENC–

1.6V

VTHRESHOLD = 1.6V

ENC+

0.1

µF

LTC2232/

LTC2233

22323 F12b

ENC–

ENC+

130

Ω

3.3V

130

Ω

MC100LVELT22

LTC2232/

LTC2233

Ω

Figure 13. Digital Output Buffer

LTC2232/LTC2233

22323 F13

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

D9 – D0

(2V Range)

(Offset Binary)

(2’s Complement)

>+1.000000V

11 1111 1111

01 1111 1111

+0.998047V

11 1111 1111

01 1111 1111

+0.996094V

11 1111 1110

01 1111 1110

+0.001953V

10 0000 0001

00 0000 0001

0.000000V

10 0000 0000

00 0000 0000

–0.001953V

01 1111 1111

11 1111 1111

–0.003906V

01 1111 1110

11 1111 1110

–0.998047V

00 0000 0001

10 0000 0001

–1.000000V

00 0000 0000

10 0000 0000

<–1.000000V

00 0000 0000

10 0000 0000

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