SN74ALVC7813

64

× 18

LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS594A – OCTOBER 1997 – REVISED APRIL 1998

1

POST OFFICE BOX 655303

Widebus

™ Family

Be Asynchronous or Coincident

to Independent System Clocks

Almost-Full/Almost-Empty Flag

Expansion Without Additional Logic

Clock

Clock

Load and All Data Outputs Switching

Simultaneously

SN74ACT7805, and SN74ACT7813

Package Using 25-mil Center-to-Center

Lead Spacing

description

The SN74ALVC7813 is suited for buffering

asynchronous data paths up to 50-MHz clock

rates and 13-ns access times. This device is

devices can be configured for bidirectional data

buffering without additional logic.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,

regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output

buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at

least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO

initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO

must be reset upon power up.

The SN74ALVC7813 is characterized for operation from 0

°C to 70°C.

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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RESET

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

GND

D7

D6

D5

D4

D3

D2

D1

D0

HF

PEN

AF/AE

WRTCLK

WRTEN2

WRTEN1

IR

OE1

Q17

Q16

Q15

GND

Q14

Q13

Q12

Q11

Q10

Q9

GND

Q8

Q7

Q6

Q5

Q4

Q3

Q2

GND

Q1

Q0

RDCLK

RDEN

OE2

OR

DL PACKAGE

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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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