Integrated Circuits Inc.

aP89021/010

Ver 2.2

May 31, 2007

14

TIMING WAVEFORMS

DD = 3.3V, VSS = 0V, 8KHz sampling )

Symbol

Parameter

Min.

Typ.

Max.

Unit

Note

tKD

Key trigger debounce time

16





ms

1

tKD

Key trigger debounce time – retrigger

24





ms

1

tSTPD

STOP pulse output delay time





256

μs

tSTPW

STOP pulse width



64



ms

1

tBD

BUSY signal output delay time





100

ns

tBH

BUSY signal output hold time



100



ns

tAS

Address set-up time

100





ns

tAH

Address hold time

100





ns

tSBTW

SBT stroke pulse width

16





ms

1

tLEDC

LED flash frequency



3



Hz

2

Notes :

1.

This parameter is inversely proportional to the sampling frequency.

2.

This parameter is proportional to the sampling frequency.

S1~S4, SBT

STOP

COUT

BUSY

KEY Trigger Mode

CPU Parallel Mode

Addr.

S1~S4

SBT