SN74ACT3632

512

× 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

23

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

VCC = 4.5 V,

IOH = – 4 mA

2.4

V

VOL

VCC = 4.5 V,

IOL = 8 mA

0.5

V

II

VCC = 5.5 V,

VI = VCC or 0

±5

µA

IOZ

VCC = 5.5 V,

VO = VCC or 0

±5

µA

ICC

VCC = 5.5 V,

VI = VCC – 0.2 V or 0

400

µA

‡

CSA = VIH

A0 – A35

0

‡

V5 5 V

O

i

t t 3 4 V

CSB = VIH

B0 – B35

0

∆ICC‡

VCC = 5.5 V,

One input at 3.4 V,

Other inputs at VCC or GND

CSA = VIL

A0 – A35

1

mA

CC

Other in uts at VCC or GND

CSB = VIL

B0 – B35

1

All other inputs

1

Ci

VI = 0,

f = 1 MHz

4

pF

Co

VO = 0,

f = 1 MHz

8

pF

† All typical values are at VCC = 5 V, TA = 25°C.

‡ This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Figures 1 through 17)

’ACT3632-15

’ACT3632-20

’ACT3632-30

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency, CLKA or CLKB

66.7

50

33.4

MHz

tc

Clock cycle time, CLKA or CLKB

15

20

30

ns

tw(CLKH)

Pulse duration, CLKA and CLKB high

6

8

10

ns

tw(CLKL)

Pulse duration, CLKA and CLKB low

6

8

10

ns

tsu(D)

Setup time, A0 – A35 before CLKA

↑ and B0–B35 before CLKB↑

4

5

6

ns

tsu(EN)

Setup time, CSA, W/RA, ENA, and MBA before CLKA

↑; CSB,

W/RB, ENB, and MBB before CLKB

↑

4.5

5

6

ns

tsu(RS)

Setup time, RST1 or RST2 low before CLKA

↑ or CLKB↑§

5

6

7

ns

tsu(FS)

Setup time, FS0 and FS1 before RST1 and RST2 high

7.5

8.5

9.5

ns

th(D)

Hold time, A0 – A35 after CLKA

↑ and B0–B35 after CLKB↑

1

1

1

ns

th(EN)

Hold time, CSA, W/RA, ENA, and MBA after CLKA

↑; CSB, W/RB,

ENB, and MBB after CLKB

↑

1

1

1

ns

th(RS)

Hold time, RST1 or RST2 low after CLKA

↑ or CLKB↑§

4

4

5

ns

th(FS)

Hold time, FS0 and FS1 after RST1 and RST2 high

2

3

3

ns

tsk1¶

Skew time between CLKA

↑ and CLKB↑ for ORA, ORB,

IRA, and IRB

7.5

9

11

ns

tsk2¶

Skew time between CLKA

↑ and CLKB↑ for AEA, AEB,

AFA, and AFB

12

16

20

ns

§ Requirement to count the clock edge as one of at least four needed to reset a FIFO

¶ Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and

CLKB cycle.