KH600

DATA SHEET

REV. 2 January 2004

11

than 10V. This will not effect supply current because as Figure 11

Layout Considerations

General layout and supply bypassing play major roles in high

frequency performance. Cadeka has evaluation boards to use

as a guide for high frequency layout and as aid in device testing

and characterization. Follow the steps below as a basis for

high frequency layout:

• Include all recommended 6.8

µF and 0.01µF

bypass capacitors

• Place the 6.8

µF capacitors within 0.75 inches of

the power pin

• Place the 0.01

µF capacitors within 0.1 inches of

the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance

• Minimize all trace lengths to reduce series inductances

• A 10pF to 50pF bypass capacitor can be used between

pins 5 and 6 and between pins 10 and 11 to reduce

crosstalk from the positive supply

Refer to the evaluation board layouts shown in Figure 22 for

more information.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of this device:

Do not include capacitors C2, C3, C7, C11, and C12

that are shown on the KEB007 evaluation board. Evaluation

board schematics and layouts are shown in Figure 22. Refer

to the schematic shown in Figure 1 for the KEB007 board

and Figure 3 for the KEB009 board.

140

40

100

120

Common Mode Output Voltage (V)

01

3

4

2

60

80

Evaluation

Description

Products

Board

KEB007

Basic KH600 Eval Bd

KH600

KEB009

KH600 Eval Bd with offset and

KH600

-30

-80

-55

-50

-45

-40

-35

Common Mode Output Voltage (V)

01

3

4

2

HD3

HD2

-75

-70

-65

-60

-40

-80

-75

-70

-65

-60

-55

-50

-45

Common Mode Output Voltage (V)

01

3

4

2

HD3

HD2

HD3

HD2