Data Sheet

©2007-2009 CADEKA Microcircuits LLC

www.cadeka.com

8

Application Information

The CLCx550 series are high gain, wide bandwidth de-

vices which, like most comparators, can easily oscillate

if the output lead is inadvertently allowed to capacitively

couple to the inputs via stray capacitance. This shows up

only during the output voltage transition intervals as the

comparator changes states. Power supply bypassing is not

required to solve this problem. Standard PC board layout

is helpful as it reduces stray input-output coupling. Reduc-

ing this input resistors to < 10kΩ reduces the feedback

signal levels and finally, adding even a small amount (1

to 10mV) of positive feedback (hysteresis) causes such a

rapid transition that oscillations due to stray feedback are

not possible. Simply socketing the IC and attaching resis-

tors to the pins will cause input-output oscillations during

the small transition intervals unless hysteresis is used. If

the input signal is a pulse waveform, with relatively fast

rise and fall times, hysteresis is not required.

All pins of any unused comparators should be tied to the

negative supply. The bias network of the CLCx550 series

establishes a drain current which is independent of the

magnitude of the power supply voltage over the range

of 2V DC to 30V DC. It is usually unnecessary to use a

bypass capacitor across the power supply line.

The differential input voltage may be larger than V+ with-

out damaging the device. Protection should be provided

to prevent the input voltages from going negative more

than −0.3V DC (at 25°C). An input clamp diode can be

used as shown in the applications section.

The output of the CLCx550 series is the uncommitted

collector of a grounded-emitter NPN output transistor.

Many collectors can be tied together to provide an output

OR’ing function. An output pull-up resistor can be con-

nected to any available power supply voltage within the

permitted supply voltage range and there is no restriction

on this voltage due to the magnitude of the voltage which

is applied to the V+ terminal of the CLCx550 package.

The output can also be used as a simple SPST switch to

ground (when a pull-up resistor is not used). The amount

of current which the output device can sink is limited by

the drive available (which is independent of V+) and the β

of this device. When the maximum current limit is reached

(approximately 16 mA), the output transistor will come

out of saturation and the output voltage will rise very rap-

idly. The output saturation voltage is limited by the ap-

proximately 60Ω RSAT of the output transistor. The low

offset voltage of the output transistor (1 mV) allows the

output to clamp essentially to ground level for small load

currents.

Layout Considerations

General layout and supply bypassing play major roles

in high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

an aid in device testing and characterization. Follow the

steps below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Products

CEB006

CLC2550

CEB018

CLC4550

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in

Figures 9-14. These evaluation boards are built for dual-

supply operation. Follow these steps to use the board in a

single-supply application:

1. Short -Vs to ground.

directly connected to the ground plane.