CDK3404 datasheet(8/11 Pages) CADEKA

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Data Sheet

The CDK3404 may also be operated with a single 75Ω

terminating resistor. To lower the output voltage swing

to the desired range, the nominal value of the resistor on

RREF should be doubled.

R, G, and B Current Outputs - IOR, IOG, IOB

Current source outputs can drive VESA VSIS, and RS-

343A/SMPTE-170M compatible levels into doubly-termi-

nated 75Ω lines. Sync pulses can be added to the green

output. When SYNC is HIGH, the current added to IOG is:

IOS = 2.33 (VREF/ RREF)

Current-Setting Resistor - RREF

Full-scale output current of each D/A converter is deter-

mined by the value of the resistor connected between

RREF and GND. Nominal value of RREF is found from:

RREF = 5.31 (VREF/IFS)

where IFS is the full-scale (white) output current (in amps)

from the D/A converter (without sync). Sync is 0.439 * IFS.

D/A full-scale (white) current may also be calculated from:

IFS = VFS/RL

Where VFS is the white voltage level and RL is the total

resistive load (Ω) on each D/A converter. VFS is the blank

to full-scale voltage.

Voltage Reference

Full scale current is a multiple of the current ISET through

an external resistor, RSET connected between the RREF pin

and GND. Voltage across RSET is the reference voltage,

VREF, which can be derived from either the 1.25 volt in-

ternal bandgap reference or an external voltage reference

connected to VREF. To minimize noise, a 0.1µF capacitor

should be connected between VREF and ground. ISET is

mirrored to each of the GBR output current sources. To

minimize noise, a 0.1µF capacitor should be connected

between the COMP pin and the analog supply voltage

VDDA.

Voltage Reference Output/Input - VREF

An internal voltage source of +1.25V is output on the VREF

pin. An external +1.25V reference may be applied to over-

ride the internal reference. Decoupling VREF to GND with

a 0.1µF ceramic capacitor is required.

Power and Ground

Required power is a single +3.3V supply. To minimize power

supply induced noise, analog +3.3V should be connected

to VDDD and VDDA pins with 0.1µF and 0.01µF decoupling

capacitors placed adjacent to each VDD pin or pin pair.

The high slew-rate of digital data makes capacitive cou-

pling to the outputs of any D/A converter a potential

problem. Since the digital signals contain high-frequency

components of the CLK signal, as well as the video out-

put signal, the resulting data feedthrough often looks

like harmonic distortion or reduced signal-to-noise perfor-

mance. All ground pins should be connected to a common

solid ground plane for best performance.

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