SN54HC166, SN74HC166

8-BIT PARALLEL-LOAD SHIFT REGISTERS

SCLS117B – DECEMBER 1982 – REVISED MAY 1997

2

POST OFFICE BOX 655303

FUNCTION TABLE

INPUTS

OUTPUTS

INPUTS

INTERNAL

CLR

SH/LD

CLK INH

CLK

SER

PARALLEL

A...H

QA

QB

QH

L

X

X

X

X

X

L

L

L

H

XL

L

X

X

QA0

QB0

QH0

H

LL

↑

X

a ...h

a

bh

H

HL

↑

HX

H

QAn

QGn

H

HL

↑

LX

L

QAn

QGn

H

X

H

↑

X

X

QA0

QB0

QH0

CLR

SRG8

R

9

M1 [Shift]

15

M2 [Load]

6

CLK INH

7

CLK

C3/1

2, 3D

3

B

4

C

5

D

10

E

11

F

12

G

14

H

1, 3D

1

SER

2, 3D

2

A

13

≥1

QH

SH/LD

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, and W packages.