ZADCS1222 datasheet(13/21 Pages) ZMD

13 / 21 page

Datasheet

ZADCS1282/1242/1222 Family

Information furnished in this publication is preliminary and subject to changes without notice.

13/21

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

IN-

IN+

Converter

SGL/DIF = HIGH

See Table 5 & Table 6

for Coding Schemes

Shown configuration

A2 … A0 = 0x000

In unipolar mode the voltage at IN+ must exceed the

voltage at IN– to obtain codes unequal to 0x000. The

entire 12 bit transfer characteristic is then covered by IN+

if IN+ ranges from IN– to (IN– +Vref). Any voltage on

IN+ > (IN– + Vref) results in code 0xFFF. Code 0xFFF is

not reached, if (IN– +Vref) > VDD + 0.2V because the

input voltage is clamped at VDD + 0.2V by ESD protec-

tion devices.

The voltage at IN– can range from -0.2V … ½ VREF with-

out limiting the Code Range, assuming the fore men-

tioned VDD condition is true. See also Figure 8 for input

voltage ranges in unipolar conversion mode.

In bipolar mode, IN+ can range from (IN– - Vref/2) to (IN–

+ Vref/2) keeping the converter out of code saturation.

For instance, if IN– is set to a constant DC voltage of

Vref/2, then IN+ can vary from 0V to VREF to cover the

entire code range. Lower or higher voltages of IN+ keep

the output code at the minimum or maximum code value.

Figure 9 shows the input voltage ranges in bipolar mode

when IN– is set to a constant DC voltage.

As explained before, converters out of the ZADCS12x2

family can also be used to convert fully differential input

signals that change around a common mode input volt-

age.

The bipolar mode is best used for such purposes since it

allows the input signals to be positive or negative in rela-

tion to each other.

The common mode level of a differential input signal is

calculated VCM = (V(IN+)+ V(IN–)) / 2. To avoid code clip-

ping or over steering of the converter, the common mode

level can change from ¼ VREF … ¾ VREF. Within this

range the peak to peak amplitude of the differential input

signal can be ± VREF/2.

The average input current on the analog inputs depends

on the conversion rate. The signal source must be capa-

ble of charging the internal sampling capacitors (typically

16pF on each input of the converter: IN+ and IN–) within

the acquisition time tACQ to the required accuracy. The

equivalent input circuit in sampling mode is shown in

Figure 6.

The following equation provides a rough hand calculation

for a source impedance RS that is required to settle out a

DC input signal referenced to AGND with 12 bit accuracy

in a given acquisition time

Figure 7: Block diagram of input multiplexer

1.5*VREF

VREF

VIN+

VIN-

VDD-VREF

Code Range

0xFFF

0x000

Figure 8: Input voltage range in unipolar mode

0.5*VREF

VREF

¾ VREF

VCM

VDIFF

+VREF/2

VCM Range

Figure 9: Input voltage range for fully differen-

tial signals in bipolar mode

¼ VREF

-VREF/2

RSW

CHOLD+

16pF

CIN

4pF

RSW

AGND

CHOLD-

16pF

CIN

4pF

AGND

IN+

IN-

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

Channel

Multiplexer

VDC

3kΩ

Figure 6: Equivalent input circuit during sampling

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