Datasheet

ZADCS146 / ZADCS147

Copyright © 2008, ZMD AG, Rev. 1.1

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The

Information furnished in this publication is preliminary and subject to changes without notice.

10/19

CH0

1

CH1

2

CH2

3

CH3

4

CH4

5

CH5

6

CH6

7

CH7

8

COM

9

nSHDN

10

VDD 20

SCLK 19

nCS 18

DIN 17

SSTRB 16

DOUT 15

DGND 14

AGND 13

ZADCS146

47nF

≥ 4.7µF

SCK

I/O

MOSI

MISO

0.1µF

10µF

µC

Single-ended or differential

analog inputs, 0V … +2.5V

+2.7V to 5.25V

Figure 2: Basic application schematic for ZADCS146

CH0

1

CH1

2

CH2

3

CH3

4

CH4

5

CH5

6

CH6

7

CH7

8

COM

9

nSHDN

10

VDD 20

SCLK 19

nCS 18

DIN 17

SSTRB 16

DOUT 15

DGND 14

AGND 13

n.c. 12

ZADCS147

≥ 4.7µF

SCK

I/O

MOSI

MISO

0.1µF

10µF

µC

Single-ended or differential

analog inputs, 0V … +2.5V

+2.7V to 5.25V

Table 3: Channel selection in Single Ended Mode

(SGL/DIF = HIGH)

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0

0

0

IN+

IN-

1

0

0

IN+

IN-

0

0

1

IN+

IN-

1

0

1

IN+

IN-

0

1

0

IN+

IN-

1

1

0

IN+

IN-

0

1

1

IN+

IN-

1

1

1

IN+

IN-

Table 4: Channel selection in Differential Mode

(SGL/DIF = LOW)

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0

0

0

IN+

IN-

0

0

1

IN+

IN-

0

1

0

IN+

IN-

0

1

1

IN+

IN-

1

0

0

IN-

IN+

1

0

1

IN-

IN+

1

1

0

IN-

IN+

1

1

1

IN-

IN+

2 DETAILED DESCRIPTION

2.1

General Operation

The ZADCS146 / ZADCS147 are classic successive

approximation register (SAR) type converters. The archi-

tecture is based on a capacitive charge redistribution

DAC merged with a resistor string DAC building a hybrid

converter with excellent monotonicity and DNL properties.

The Sample & Hold function is inherent to the capacitive

DAC. This avoids additional active components in the

signal path that could distort the input signal or introduce

errors.

Both devices ZADCS146 / ZADCS147 build on the same

converter core and differ only in the availability of an

internal reference voltage generator. ZADCS146 is

equipped with a highly accurate internal 1.25V bandgap

reference which is available at the VREFADJ pin. The

bandgap voltage is further amplified by an internal buffer

amplifier to 2.50V that is available at pin VREF.

ZADCS147 comes without the internal reference and the

internal buffer amplifier. It requires an external reference

supplied at VREF, with the benefit of considerably lower

power consumption.

A basic application schematic of ZADC146 is shown in

be operated with an external reference, if VREFADJ is

tied to VDD.

2.2

Analog Input

The analog input to the converter is fully differential. Both

diagram at front page) get sampled during the acquisition

period enabling the converter to be used in fully differen-

tial applications where both signals can vary over time.

The ZADCS146 / ZADCS147 converters do not require

that the negative input signal be kept constant within

± 0.5LSB during the entire conversion as is commonly

required by converters featuring pseudo differential op-

eration only.

The input signals can be applied single ended, refer-

enced to the COM pin, or differential, using four pairs of

the eight input channels. The desired configuration is

selectable for every conversion via the Control-Byte re-

ceived on DIN pin of the digital interface (see further

description below)

A block diagram of the input multiplexer is shown in

Control-Byte bits A2, A1, A0 and SGL/DIF to the configu-

ration of the analog multiplexer.

swing between –0.2V and VDD+0.2V. However, depend-

ing on the selected conversion mode – uniploar or bipo-

lar – certain input voltage relations can limit the output

code range of the converter.

Figure 3: Basic application schematic for ZADCS147