SN54ALS10A, SN54AS10, SN74ALS10A, SN74AS10

TRIPLE 3-INPUT POSITIVE-NAND GATES

SDAS002B – MARCH 1984 – REVISED DECEMBER 1994

Copyright

1

POST OFFICE BOX 655303

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These devices contain three independent 3-input

positive-NAND gates. They perform the Boolean

functions Y = A

• B • C or Y = A + B + C in positive

logic.

The

SN54ALS10A

and

SN54AS10

are

characterized for operation over the full military

temperature range of – 55

°C to 125°C. The

SN74ALS10A and SN74AS10 are characterized

for operation from 0

°C to 70°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

C

Y

H

H

H

L

L

XX

H

X

LX

H

X

X

L

H

logic diagram (positive logic)

&

1

1A

2

1B

13

1C

1Y

12

3

2A

4

2B

5

2C

2Y

6

9

3A

10

3B

11

3C

3Y

8

3B

1B

3A

3C

3Y

2A

2C

2Y

1Y

1C

1A

2B

1

2

13

3

4

5

9

10

11

12

6

8

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

SN54ALS10A, SN54AS10 ...J PACKAGE

SN74ALS10A, SN74AS10 ...D OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

2A

2B

2C

2Y

GND

1C

1Y

3C

3B

3A

3Y

SN54ALS10A, SN54AS10 . . . FK PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

1Y

NC

3C

NC

3B

2A

NC

2B

NC

2C

NC – No internal connection

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.