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LSN2 Series

Non-isolated, DOSA-SIP, 6/10/16A

Selectable-Output DC/DC Converters

MDC_LSN2.B06 Page 13 of 15

Notice in the simplified Sequence/Track equivalent circuit (Figure 15) that

a blocking diode effectively disconnects this circuit when the Sequence/

Power Good Output

The Power Good Output consists of an unterminated BSS138 small signal

field effect transistor and a dual window comparator input circuit driving the

gate of the FET. Power Good is TRUE (open drain, high impedance state) if the

converter’s power output voltage is within about ±10% of the setpoint. Thus,

the PG TRUE condition indicates that the converter is approximately within

regulation. Since an overcurrent condition occurs at about 2% output voltage

reduction, the Power Good does not directly measure an output overcurrent

condition at rated maximum output current. However, gross overcurrent or

an output short circuit will set Power Good to FALSE (+0.2V saturation, low

impedance condition).

Figure 15. Sequence/Track Simplified Equivalent Schematic

[6]

Allow the converter to eventually achieve its full-rated setpoint output

voltage. Do not remain in ramp up/down mode indefinitely. The converter

is characterized and meets all its specifications only at the setpoint

voltage (plus or minus any trim voltage). During the ramp-up phase, the

converter is not considered fully in regulation. This may affect perfor-

mance with excessive high current loads at turn-on.

[7]

The Sequence is a sensitive input into the feedback control loop of the

converter. Avoid noise and long leads on this input. Keep all wiring very

short. Use shielding if necessary. Consider adding a small parallel ce-

ramic capacitor across the Sequence/Track input (see Figure 14) to block

any external high frequency noise.

[8] If one converter is slaving to another master converter, there will be a very

short phase lag between the two converters. This can usually be ignored.

[9]

You may connect two or more Sequence inputs in parallel from two

converters. Be aware of the increasing pull-up bias current and reduced

input impedance.

[10] Any external capacitance added to the converter’s output may affect

ramp up/down times and ramp tracking accuracy.

Figure 16. Equivalent Power Good Circuit

Using a simple connection to external logic (and returned to the converter’s

Common connection), the Power Good output is unterminated so that the user

may adapt the output to a variety of logic families. The PG pin may therefore

be used with logic voltages which are not necessarily the same as the input

or output power voltages. Install an external pullup resistor to the logic supply

voltage which is compatible with your logic system. When the Power Good is

out of limit, the FET is at saturation, approximately +0.2V output. Keep this

LOW (FALSE) pulldown current to less than 10mA.

Please note that Power Good is briefly false during Sequence ramp-up.

Ignore Power Good while in transition.