SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

4

POST OFFICE BOX 655303

logic diagram (positive logic)

S

1D

R

C1

S

1D

R

C1

S

1D

R

C1

S

1D

R

C1

S

1D

R

C1

S

1D

R

C1

S

1D

R

C1

S

1D

R

C1

1

15

2

10

SH/LD

CLK INH

CLK

SER

9

7

QH

QH

11

12

13

14

3

4

5

6

AB

CD

E

F

G

H

Pin numbers shown are for D, J, N, NS, and W packages.

QA

QB

QC

QD

QE

QF

QG

typical shift, load, and inhibit sequences

Serial Shift

Inhibit

Load

E

Output QH

H

G

C

F

Data

Inputs

D

SH/LD

SER

CLK INH

CLK

B

A

Output QH

L

L

H

L

H

L

H

H

H

H

L

H

L

H

L

H

L

H

L

L

H

L

H

L

H

The SN54165 and SN74165 devices

are obsolete and are no longer supplied.