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HC240 датащи(PDF) 4 Page - Altera Corporation

номер детали HC240
подробное описание детали  HardCopy II Device Family
PDF  228 Pages
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производитель  ALTERA [Altera Corporation]
домашняя страница  http://www.altera.com
Logo ALTERA - Altera Corporation

HC240 датащи(HTML) 4 Page - Altera Corporation

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Altera Corporation
Preliminary
September 2008
HardCopy Series Handbook, Volume 1
■
System performance up to 350 MHz
■
Up to 50% power reduction (dynamic and static) for typical designs
compared to Stratix II FPGA prototypes
1
The actual performance and power consumption improvements
mentioned in this datasheet are design-dependent.
■
Internal Memory
●
Up to 8,847,360 RAM bits available (including parity bits)
●
True dual-port memory, suitable for use in first-in-first-out
(FIFO) buffers
■
Phase-Locked Loops (PLLs)
●
Up to 16 global clocks with 24 clocking resources per device
region
●
Clock control block supports dynamic clock network
enable/disable and dynamic global clock network source
selection
●
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per
device which provide identical features as the FPGA
counterparts, including spread spectrum, programmable
bandwidth, clock switchover, real-time PLL reconfiguration,
advanced multiplication, and phase shifting
■
I/O Standards and Intellectual Property (IP)
●
Support for numerous single-ended and differential I/O
standards such as LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL,
and LVDS
●
High-speed differential I/O support on up to 116 channels with
dynamic phase alignment (DPA) circuitry for
1-Gigabit-per-second (Gbps) performance
●
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
●
Support for high-speed external memory, including DDR and
DDR2 SDRAM, RLDRAM II, QDRII SRAM, and SDR SDRAM
●
Support for multiple intellectual property megafunctions from
Altera MegaCore® functions, and Altera Megafunction Partners
Program (AMPPSM) megafunctions
■
Packaging
●
Pin-compatible with Stratix II FPGA prototypes
●
Up to 951 user I/O pins available
●
Available in wire bond and flip-chip space-saving
FineLine BGA packages (Table 1–3).



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