This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

21

EN25F05

Rev. B, Issue Date: 2008/06/23

Power-up Timing

Figure 21. Power-up Timing

Table 7. Power-Up Timing and Write Inhibit Threshold

Symbol

Parameter

Min.

Max.

Unit

tVSL(1)

VCC(min) to CS# low

10

µs

tPUW(1)

Time delay to Write instruction

1

10

ms

VWI(1)

Write Inhibit Voltage

1

2.5

V

Note:

1.The parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).

The Status Register contains 00h (all Status Register bits are 0).