MSP430x11x

MIXED SIGNAL MICROCONTROLLERS

SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

14

POST OFFICE BOX 655303

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

VIT+

Positive-going input threshold voltage

VCC = 3 V

1.2

2.1

V

VIT+

Positive-going input threshold voltage

VCC = 5 V

2.3

3.4

V

VIT−

Negative-going input threshold voltage

VCC = 3 V

0.7

1.5

V

VIT−

Negative-going input threshold voltage

VCC = 5 V

1.4

2.3

V

Vhys

Input voltage hysteresis, (VIT+ − VIT−)

VCC = 3 V

0.3

1

V

Vhys

Input voltage hysteresis, (VIT+ − VIT−)

VCC = 5 V

0.6

1.4

V

standard inputs RST/NMI, TCK, TMS, TDI

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

VIL

Low-level input voltage

VCC = 3 V/5 V

VSS

VSS+0.8

V

VIH

High-level input voltage

VCC = 3 V/5 V

0.7xVCC

VCC

V

inputs Px.x, TAx

PARAMETER

TEST CONDITIONS

VCC

MIN

NOM

MAX

UNIT

Port P1, P2: P1.x to P2.x,

3 V/ 5 V

1.5

cycle

t(int)

External Interrupt timing

Port P1, P2: P1.x to P2.x,

External trigger signal for the interrupt flag, (see Note 1)

3 V

540

ns

t(int)

External Interrupt timing

External trigger signal for the interrupt flag, (see Note 1)

5 V

270

ns

3 V/ 5 V

1.5

cycle

t(cap)

Timer_A, capture timing

TA0, TA1, TA2. (see Note 2)

3 V

540

ns

t(cap)

Timer_A, capture timing

TA0, TA1, TA2. (see Note 2)

5 V

270

ns

NOTES:

1. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with

trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set.

2. The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A

capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure

a correct capture of the 16-bit timer value and to ensure the flag is set.

internal signals TAx, SMCLK at Timer_A

PARAMETER

TEST CONDITIONS

VCC

MIN

NOM

MAX

UNIT

f(IN)

Input frequency

Internal TA0, TA1, TA2, tH = tL

3 V

dc

10

MHz

f(IN)

Input frequency

Internal TA0, TA1, TA2, tH = tL

5 V

dc

15

MHz

f(TAint)

Timer_A clock frequency

Internally, SMCLK signal applied

3 V/5 V

dc

fSystem

leakage current (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Ilkg(Px.x)

High-impendance leakage current

Port P1: P1.x, 0

≤ ×≤ 7

(see Note 2)

VCC = 3 V/5 V,

±50

nA

Ilkg(Px.x)

High-impendance leakage current

Port P2: P2.x, 0

≤ ×≤ 5

(see Note 2)

VCC = 3 V/5 V,

±50

nA

NOTES:

1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional

pullup or pulldown resistor.