CDC536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS378F – APRIL 1994 – REVISED OCTOBER 1998

7

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

LOAD CIRCUIT FOR OUTPUTS

CL = 30 pF

(see note A)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

tphase error

1.5 V

1.5 V

3 V

0 V

1.5 V

VOH

VOL

Input

0.8 V

2 V

tr

tf

0.8 V

2 V

Output

500

W

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 100 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms