CDC2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS597 – DECEMBER 1997

1

POST OFFICE BOX 655303

Synchronous DRAM Applications

Ten Outputs

Ten Outputs

Synchronize the Outputs to the Clock Input

Small-Outline Package

description

The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to

precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It

integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output

enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input

is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

The CDC2510 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

G

CLK

1Y

(0:9)

FBOUT

X

L

L

L

L

HL

H

H

H

H

H

Copyright

© 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLK

1Y9

1Y8

GND

GND

1Y7

1Y6

1Y5

FBIN

1

2

3

4

5

6

7

8

9

10

11

12

AGND

1Y0

1Y1

1Y2

GND

GND

1Y3

1Y4

G

FBOUT

24

23

22

21

20

19

18

17

16

15

14

13

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