1

Data sheet acquired from Harris Semiconductor

SCHS135

Features

• True and Complementary Outputs

• Buffered Inputs and Outputs

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Description

The Harris CD74HC75 and CD74HCT75 are dual 2-bit

bistable transparent latches. Each one of the 2-bit latches is

controlled by separate Enable inputs (1E and 2E) which are

active LOW. When the Enable input is HIGH data enters the

latch and appears at the Q output. When the Enable input

(1E and 2E) is LOW the output is not affected.

Pinout

CD74HC75, CD74HCT75

(PDIP, SOIC)

TOP VIEW

Ordering Information

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

1Q0

1D0

1D1

2E

2D0

2Q1

2D1

1Q0

1Q1

1E

GND

2Q0

2Q0

2Q1

1Q1

March 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1666.1

CD74HC75,

CD74HCT75

Dual 2-Bit Bistable

Transparent Latch

[ /Title

(CD74

HC75,

CD74

HCT75

)

/Sub-

ject

(Dual

2-Bit

Bistabl

e