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Description

The Harris CD74HC652 and CD74HCT652 three-state, octal-

bus transceiver/registers use silicon-gate CMOS technology

to achieve operating speeds similar to LSTTL with the low

power consumption of standard CMOS integrated circuits.

The CD74HC652 and CD74HCT652 have non-inverting

outputs. These devices consists of bus transceiver circuits, D-

type flip-flops, and control circuitry arranged for multiplexed

transmission of data directly from the data bus or from the

are provided to control the transceiver functions. SAB and

SBA control pins are provided to select whether real-time or

stored data is transferred. The circuitry used for select control

will eliminate the typical decoding glitch that occurs in a

multiplexer during the transition between stored and real-time

data. A LOW input level selects real-time data, and a HIGH

selects stored data. The following examples demonstrates the

four fundamentals bus-management functions that can be

performed with the octal-bus transceivers and registers.

Data on the A or B data bus, or both, can be stored in the

internal D flip-flops by low-to-high transitions at the appropriate

clock pins (CAB or CBA) regardless of the select of the control

pins. When SAB and SBA are in the real-time transfer mode, it

is also possible to store data without using the D-type flip-flops

configuration, each output reinforces its input. Thus, when all

other data sources to the two sets of bus lines are at high

impedance, each set of bus lines will remain at its last state.

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG.

NO.

CD74HC652EN

-55 to 125

24 Ld PDIP

E24.3

CD74HCT652M

-55 to 125

24 Ld SOIC

M24.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die is available which meets all electrical

specifications. Please contact your local sales office or Harris

customer service for ordering information.

CD74HC652, CD74HCT652

CD74HC652, CD74HCT652