2

P/N: PM1239

REV. 1.7, AUG. 15, 2008

MX25L2005

HARDWARE FEATURES

• SCLK Input

• SI Input

• SO Output

• WP# pin

• HOLD# pin

• PACKAGE

- All Pb-free devices are RoHS Compliant

GENERAL DESCRIPTION

The MX25L2005 is a CMOS 2,097,152 bit serial Flash memory, which is configured as 262,144 x 8 internally. The

MX25L2005 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three

bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is

enabled by CS# input.

The MX25L2005 provide sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified

page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase

command is executes on chip or sector(4K-bytes) or block(64K-bytes).

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current.

The MX25L2005 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program

and erase cycles.