LTC4217CDHC datasheet(13/18 Pages) LINER

13 / 18 page

LTC4217

4217fc

APPLICATIONS INFORMATION

12V Fixed Version

In the LTC4217-12 the UV, OV and FB pins are driven by

internal dividers which may need to be ﬁltered to prevent

false faults. By placing a bypass capacitor on these pins

the faults are delayed by the RC time constant. Use the

RIN value from the electrical characteristics table for this

calculation.

In cases where the ﬁxed thresholds need a slight adjust-

ment, placing a resistor from the UV or OV pins to VDD

or GND will adjust the threshold up or down. Likewise

placing a resistor between FB pin to OUT or GND adjusts

the threshold. Again use the RIN value from the electrical

characteristics table for this calculation.

An example in Figure 5 raises the UV turn-on voltage from

9.88V to 10.5V. Increasing the UV level requires adding a

resistor between UV and ground. The resistor, RSHUNT1,

can be calculated using electrical table parameters as

follows:

RSHUNT1 =

R IN

() •VOLD

VNEW –VOLD

()

18k • 9.88

10.5 – 9.88

()

= 287k

In this same ﬁgure the OV threshold is lowered from

15.05V to 13.5V. Decreasing the OV threshold requires

adding a resistor between VDD and OV. This resistor can

be calculated as follows:

RSHUNT2 =

R IN

() •VOLD

V TH

()

VNEW –VOV TH

()

VOLD –VNEW

()

⎛

⎝

⎜

⎞

⎠

⎟

18k • 15.05

1.235

13.5 – 1.235

()

15.05 – 13.5

()

⎛

⎝⎜

⎞

⎠⎟

= 1.736M

Use the equation for RSHUNT1 for increasing the OV and

FB thresholds. Likewise use the equation for RSHUNT2 for

decreasing the UV and FB thresholds.

Design Example

Consider the following design example (Figure 6): VIN =

12V, IMAX = 2A. IINRUSH = 100mA, CL = 330μF, VUVON =

9.88V, VOVOFF=15.05V,VPWRGD=10.5V.Acurrentlimitfault

triggers an automatic restart of the power-up sequence.

Figure 5. Adjusting LTC4217-12 Thresholds

4217 F05

LTC4217-12

RSHUNT1

RSHUNT2

VDD

Figure 6. 1.5A, 12V Card Resident Application

ADC

0.1μF

12V

VOUT

12V

1.5A

20k

4217 F06

10k

330μF

VDD

OUT

GND

IMON

LTC4217-12DHC

INTVCC

TIMER

FLT

12V

The inrush current is deﬁned by the current required to

charge the output capacitor using the ﬁxed 0.3V/ms GATE

charge-up rate. The inrush current is deﬁned as:

IINRUSH = CL •

0.3V

⎛

⎝⎜

⎞

⎠⎟ =

330µF •

0.3V

⎛

⎝⎜

⎞

⎠⎟ =

100mA

As mentioned previously the charge-up time is the out-

put voltage (12V) divided by the output rate of 0.3V/ms

resulting in 40ms. The peak power dissipation of 12V at

100mA (or 1.2W) is within the SOA of the pass MOSFET for

40ms (see MOSFET SOA curve in the Typical Performance

Characteristics section).

NextthepowerdissipatedintheMOSFETduringovercurrent

must be limited. The active current limit uses a timer to

prevent excessive energy dissipation in the MOSFET. The

worst-case power dissipation occurs when the voltage

versus current proﬁle of the foldback current limit is at

the maximum. This occurs when the current is 2A and the

voltage is one half of the 12V or 6V. See the Current Limit

Sense Voltage vs FB Voltage in the Typical Performance

Characteristics section to view this proﬁle. In order to

survive 12W, the MOSFET SOA dictates a maximum time

of 10ms (see SOA graph). Use the internal 2ms timer

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