LTC3834-1 datasheet(8/28 Pages) LINER

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LTC3834-1

38341f

FU CTIO AL DIAGRA

SWITCH

LOGIC

–

VIN

INTVCC-0.5V

0.8V

BURSTEN

CLK

–

INTERNAL

SUPPLY

RLP

CLP

PLLIN/MODE

INTVCC

SGND

LDO

5.25V

SHDN

SLEEP

0.4V

TOP

BOOST

CIN

PGND

BOT

INTVCC

VIN

COUT

VOUT

3834-1 FD

RSENSE

VFB

DROP

OUT

DET

BOT

TOP ON

OSCILLATOR

PHASE DET

PLLLPF

PLLIN/MODE

BURSTEN

0.88V

0.80V

TRACK/SS

VFB

0.5

μA

–

TRACK/SS

ITH

CC2

CSS

2(VFB)

0.45V

SLOPE

COMP

6mV

–

SENSE–

SENSE+

ICMP

RUN

–

FIN

SHDN

ler functions, reducing the quiescent current that the

LTC3834-1 draws to approximately 4μA.

SENSE– (Pin 14/Pin 14): The (–) Input to the Differential

Current Comparator.

SENSE+ (Pin 15/Pin 15): The (+) Input to the Differential

Current Comparator. The ITH pin voltage and controlled

offsets between the SENSE– and SENSE+ pins in conjunc-

tion with RSENSE set the current trip threshold.

PLLIN/MODE (Pin 16/Pin 16): External Synchronization

Input to Phase Detector and Forced Continuous Control

Input. When an external clock is applied to this pin, the

phase-locked loop will force the rising TG signal to be

synchronized with the rising edge of the external clock. In

this case, an R-C filter must be connected to the PLLLPF

pin. When not synchronizing to an external clock, this

input determines how the LTC3834-1 operates at light

loads. Pulling this pin below 0.7V selects Burst Mode

operation. Tying this pin to INTVCC forces continuous

inductor current operation. Tying this pin to a voltage

greater than 0.9V and less than INTVCC selects pulse-

skipping operation.

Exposed Pad (Pin 17, DHC Package): SGND. Must be

soldered to PCB.

PI FU CTIO S (DHC Package/GN Package)

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