FD5T Series Programmable

CMOS Clock Oscillator

November 2008

www.pletronics.com

425-776-1880

3

Each PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the

modulation of the output frequency by a user-set amount. The modulation can be centered on the

output frequency or down side only. Which of the 1 of 8 SS settings is being used is set by the Sx input

and the user definition. The value is a percentage of the output frequency that will be modulated.

SS Option

Down Side Modulation

Centered Modulation

0

No SS

No SS

1

-0.25%

+

_0.25%

2

-0.50%

+

_0.50%

3

-0.75%

+

_0.75%

4

-1.00%

+

_1.00%

5

-1.25%

+

_1.25%

6

-1.50%

+

_1.50%

7

-2.00%

+

_2.00%

Divider Section

The dividers operate on the output of the PLL. The divider on the PLL can divide by 1 through 127, the

value is user defined. There is only 1 setting allowed per divider. These are not set by the Sx input

state.

The dividers add very little jitter to the output signals.

Multiplexers

MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from

PLL Multiplier #1. MUX #3 connect various divider outputs to the output buffer.

The device can make only one of the setting of connections shown in the block diagram (only one

pattern stored in eePROM).

Output Buffer

The output buffer can have 3 modes of operation:

1) Tri State

2) Active Low

3) The signal output of the Multiplexer

There can be two options stored for the Output Buffer, State 0 and State 1. The four Sx input settings

can have assigned one of the two Output Buffer states for each of Output Buffer sets.

Control Inputs

The two inputs, S1/SDA and S2/SCL can be configured in two ways.

1)

Used as 2 user inputs to permit up to 4 states, Sx input setting.

2)

The SDA and SCL become clock and data inputs to write to the FD5T internal setting memory.

The interface follows the I

sets the operation. (Not allowed if the VCXO function is specified.)