74ACT11286

9-BIT PARITY GENERATOR/CHECKER

WITH BUS DRIVER PARITY I/O PORTS

SCAS069B – AUGUST 1988 – REVISED APRIL 1996

5

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

2

× VCC

500

Ω

500

Ω

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

2

× VCC

GND

GND

Open

TEST

S1

tPHL

tPLH

1.5 V

1.5 V

3 V

0 V

50% VCC

50% VCC

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2

× VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

[ VCC

0 V

50% VCC

20% VCC

50% VCC

80% VCC

[ 0 V

3 V

VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms