BLOCK DIAGRAM

TIMING DIAGRAM

Note : Latches are level sensitive, not rising edges sensitive and not synchronous CLOCK.

Input of LATCH-terminal to H Level, data passes latches, and input of LATCH -terminal to L level, data

hold latches.

Input of ENABLE-terminal to H Level, all output (OUT0 ~ 7) do off.

SAMHOP Microelectronics Corp.

8-BIT CONSTANT CURRENT LED DRIVER

V.2.10

Page 5

R-EXT

ENABLE

LATCH

SERIAL-IN

CLOCK

SERIAL-

OUT

I-REG.

OUT0

OUT1

OUT7

Q

ST D

Q

ST D

Q

ST D

D Q

CK

D Q

CK

D Q

CK

CLOCK

SERIAL-IN

LATCH

ENABLE

OUT0

OUT1

OUT2

OUT7

SERIAL-OUT

0V

5V

0V

0V

5V

0V

5V

Off

On

Off

5V

Off

Off

On

0V

5V

On

On

D Q

CK