LTC3705IGN datasheet(11/20 Pages) LINER

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LTC3705

3705fb

completes the soft-start interval. In order to ensure that

control is properly transferred from the LTC3705 (pri-

mary-side) to the LTC3706 (secondary-side), it is neces-

sary to limit the rate of rise on the primary-side soft-start

ramp so that the LTC3706 has adequate time to wake up

and assume control before the output voltage gets too

high. This condition is satisfied for many applications if the

following relationship is maintained:

CSS,SEC ≤ CSS_PRI

However, care should be taken to ensure that soft-start

transfer from primary-side to secondary-side is com-

pleted well before the output voltage reaches its target

value. A good design goal is to have the transfer completed

when the output voltage is less than one-half of its target

value. Note that the fastest output voltage rise time during

primary-side soft-start mode occurs with minimum load

current.

The open-loop start-up frequency on the LTC3705 is set

by placing a resistor RFS(S) from the FS/IN– pin to GND.

Although the exact start-up frequency on the primary side

is not critical, it is generally a good practice to set it

approximately equal to the operating frequency on the

secondary side.

In this mode the start-up frequency of the LTC3705 is

approximately:

PRI

FS S

34 109

10 000

•

()

In the event that the LTC3706 fails to start up properly and

assume control of switching, there are several fail-safe

mechanisms to help avoid overvoltage conditions. First,

the LTC3705 implements a volt-second clamp that may be

used to keep the primary-side duty cycle at a level that

does not produce an excessive output voltage. Second,

the timeout of the linear regulator (described in the follow-

ing section) means that, unless the LTC3706 starts and

supports the LTC3705’s gate drives through the pulse

transformer and on-chip rectifier, the LTC3705 eventually

suffers a gate drive undervoltage fault. Finally, the LTC3706

has an independent overvoltage detection circuit that

crowbars the output of the DC/DC converter using the

synchronous secondary-side MOSFET switch.

APPLICATIO S I FOR ATIO

Figure 2. Resistive Voltage Divider for

UVLO and Optional Run/Stop Control

VIN

RUN/STOP

CONTROL

(OPTIONAL)

UVLO

GND

LTC3705

3705 F02

Linear Regulator

The linear regulator eliminates the long start-up times

associated with a conventional trickle charger by using an

external NMOS to quickly charge the capacitor connected

to the VCC pin.

Note that a trickle charger usually requires a large capaci-

tor to provide holdup for the VCC pin while the converter

attempts to start. The linear regulator in the LTC3705 can

both charge the capacitor connected to the VCC pin and

provide primary-side gate-drive bias current. Therefore,

with the linear regulator, the capacitor need only be large

enough to cope with the ripple current from driving the top

and bottom gates and holdup need not be considered.

The external NMOS for the linear regulator should be a

standard 3V threshold type (i.e. not a logic level thresh-

old). The rate of charge of VCC from 0V to 8V is controlled

by the LTC3705 to be approximately 45

µs regardless of

the size of the capacitor connected to the VCC pin. The

charging current for this capacitor is approximately:

C =

The safe operating area (SOA) for the external NMOS

should be chosen so that capacitor charging does not

damage the NMOS. Excessive values of capacitor are

unnecessary and should be avoided.

Start-Up Considerations

When used in a self-starting converter with the LTC3706,

the LTC3705 initially begins the soft-start of the converter

in an open-loop fashion. After bias is obtained on the

secondary side, the LTC3706 assumes control and

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