LTC2926IGN datasheet(19/28 Pages) LINER

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LTC2926

2926fa

have 1% tolerance. The 3-step design procedure detailed

above can be used to determine component values. Only

the slave 1 supply is considered here, as the procedure

is the same for the slave 2 supply.

1. Set the ramp rate of the master signal.

From Equation 1:

MGATE ==

100

2. Choose the feedback resistors based on the slave supply

voltage and slave load.

RL = 150Ω

From Equation 2:

RFB ≥ 100 • 150Ω = 15kΩ

Choose RFB = 15.0kΩ.

From Equation 3:

FA <•

⎛

⎝⎜

⎞

⎠⎟

−

⎛

⎝⎜

⎞

⎠

15 0

099

101

198

0 784

Ω

⎟⎟ = 964

Ω

Choose RFA = 9.53kΩ.

3. Solve for the tracking resistors that set the desired ramp

rate and voltage offset or time delay of the slave supply.

From Equation 4:

TB =•

⎛

⎝⎜

⎞

⎠⎟

15 0

100

15 0

ΩΩ

Since no offset or delay is required, Equation 5c applies:

ΔV = 0V

From Equation 6:

TA =

+−+

15 0

953

15 0

ΩΩΩ 115 0

953

Ω

In this example, all supplies remain low while the ON pin

is held below 1.23V. When the ON pin rises above 1.23V,

10µA pulls up CMGATEandthegateofMOSFETQ0at100V/s.

The source of Q0 follows the gate and pulls up the output

to 3.3V at the rate of 100V/s. This output serves as the

master ramp and is buffered from the RAMP pin to the

RAMPBUF pin. As the master output and the RAMPBUF

pin rise, the current from the TRACK pins is reduced. Con-

sequently, the voltage at the FB pins begins to fall below

0.8V, which causes the SGATE pins to rise. The sources

of the slave supply MOSFETs, Q1 and Q2, follow the rising

SGATE signals, and the slave supplies track the master

supply. When all the supplies have ﬁnished ramping, the

RSGATE pin voltage rises to close the integrated remote

sense switches, which allows the slave supply modules

to compensate for voltage drops in the series MOSFETs. If

the supplies have ramped within the power good timeout

period (about 123ms in this example), the STATUS/PGI

pin will rise, indicating completed ramping. When the

ON pin is again pulled below 1.23V, the STATUS/PGI pin

falls and the RSGATE pin falls, which opens the remote

sense switches. Next, 10µA will pull down CMGATE and the

gate of MOSFET Q0 at 100V/s. If the loads on the outputs

are sufﬁcient, all outputs will track down coincidently at

100V/s.

APPLICATIO S I FOR ATIO

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